Method of manufacturing semiconductor device with plated bump

ABSTRACT

This invention relates to a method for manufacturing a resin molded semiconductor device. According to the manufacturing method of this invention, at first an insulation film with openings at bump formed positions is applied on a semiconductor wafer having aluminium wiring thereon, then a plating ground metal layer is formed on the insulation film, then a photo resist layer with openings at bump formed positions is masked over the plating ground metal layer, then an easily bonded metal with drawing out leads such as a wire is plated at bump formed positions on the plating ground metal layer to form bumps, then the photo resist layer and the plating ground metal layer locating at those positions other than bump formed positions are removed to complete a semiconductor chip, then the semiconductor chip is bonded to a lead frame or a circuit substrate, then the drawing out leads such as a wire are bonded to the bumps on the semiconductor chip to complete a semiconductor bump chip, and finally the semiconductor bump chip is passivation-treated using passivation glass. Furthermore, a photo resist layer with openings at bump formed positions may be masked over the insulation film prior to forming the plating ground metal layer.

DESCRIPTION

1. Technical Field

This invention relates to a resin-molded semiconductor device used forelectric circuits, and more particularly, to a semiconductor device withplated bumps having a sealing structure which can prevent an externalenvironment atmosphere from invading through the contact surfaces with aresin mold at the lead drawing out portions thereof.

2. Background Art

In the field of semiconductor devices, according to a well known priormethod for drawing out leads from active and passive elements in asemiconductor chip to the exterior, aluminium is first evaporated on thesurface of the chip to form internal wiring and bonding regions. Eachsuch lead such as a wire, is bonded to a lead frame or a circuitsubstrate by ultrasonic bonding, thermo compression bonding or othertechniques, and then a resin mold is formed around the chip to encloseand complete the semiconductor device.

More specifically, when manufacturing a DIP type resin-moldedsemiconductor device as shown in FIG. 1, an oxide film 4 is formed on asemiconductor chip 1 with a collector region 12 and a base region 3. Analuminium layer 5 is applied thereon to form internal wiring and bondingregions, as shown in FIG. 3. Then, a passivation film 6 is coatedthereover to protect the overall surface, except for the aluminiumbonding regions. That portion of the aluminium layer 5 serving asbonding pads is connected to a lead frame 8 or to a circuit substrateusing drawing out leads such as a wire 7. A resin mold 9 is formedaround the chip to obtain the complete semiconductor device.

In a semiconductor device arranged as above, however, the aluminiumbonding pad 5 to which the drawing out lead such as the wire 7 isconnected has size of 80˜150 μm square, while the wire 7 has a thicknessof 25˜30 μm in diameter. Therefore, the semiconductor device is sealedby the resin mold 9 such that the aluminium surface of the pad 5 isexposed, at least at positions other than the connected portion of thewire 7 to the aluminium bonding pad 5. In this manner, even if the leadframe 8, wire 7 and semiconductor chip 1 have been sealed by the resinmold 9, there will appear gaps with age at the sealing contact surfacewith the resin depending on environmental conditions such astemperature, moisture or various gases, to which the semiconductordevice will be subjected, thereby resulting in a partially unsealedstate. When moisture or various gases enter along the lead frame 8 andwire 7 from these gaps and reach the aluminium bonding pad 5, "purpleplague" phenomenon will occur in the bonding pad where the aluminiumsurface is exposed, and this may cause breaking of the semiconductordevice. Furthermore, another drawback also has been experienced suchthat although the surface of the semiconductor chip 1 is protected bythe passivation film 6, for example an oxide film, phosphorous glassfilm or nitride film, the film itself is very thin and often includespin holes therein, whereby moisture or gas having entered therethroughcauses insulation breakdown on the surface of the semiconductor chip atlocations other than at the bonding pad.

It is therefore an object of this invention to provide a method ofmanufacturing a semiconductor device in which such purple plaguephenomenon or insulation breakdown will not occur, and which method canbe easily applied.

SUMMARY OF THE INVENTION

A method of manufacturing a semiconductor device with plated bumpsaccording to this invention comprises a first step in which aninsulation film with openings at bump formed positions is applied on asemiconductor wafer having aluminium wiring thereon, a second step inwhich a plating ground metal layer is formed on the insulation film, athird step in which a photo resist layer with openings at bump formedpositions is masked over the plating ground metal layer, a fourth stepin which an easily bonded metal with drawing out leads such as a wire isplated at bump formed positions on the plating ground metallayer to formbumps, a fifth step in which the photo resist layer and the platingground metal layer located at those positions other than the bump formedpositions are removed to complete a semiconductor chip, a sixth step inwhich the semiconductor chip is bonded to a connecting device, such aslead frame or a circuit substrate, a seventh step in which the drawingout leads such as a wire are bonded to the bumps on the semiconductorchip to complete a semiconductor bump chip, and an eighth step in whichthe semiconductor bump chip is passivation-treated using passivationglass. In the semiconductor device made by the manufacturing methodaccording to this invention, the bumps to be led out to the exterior forenergizing are fully covered with the plating ground metal on thesurface which includes the aluminium wiring, so that purple plaguephenomenon will not occur. Also, even when an easily oxidizable metal isused for the plating ground metal, conduction breakdown will not occurbecause of passivation treatment, and, furthermore, insulation breakdownwill not occur due to the surface of the semiconductor chip beingpassivation-treated. Furthermore, when prior art semiconductor chipswith plated bumps are handled or operated upon, the wire loops, afterbeing bonded, are prone to contact with each other, to suffer edgetouching, or to suffer a twist failure. These problems can arise frombad connection with the lead frame, instability of resin mold techniqueapplied after loading the chip on the circuit substrate, and failure ofthe resin mold itself. In the manufacturing method of the presentinvention, however, the passivation treatment is carried out after wirebonding, so that reduction in yield can be avoided irrespective ofinstability of the resin mold. Therefore, semiconductor devices withhigh reliability can be obtained.

In addition, this invention may include a ninth step prior to the secondstep mentioned above, in which a photo resist layer with openings atbump formed positions is masked over the foregoing insulation film. Inthis case, the plating ground metal layer to be applied in the secondstep is first formed on the photo resist layer masked in the ninth step.

BRIEF DESCRIPTION OF DRAWINGS

With the above and other objects and advantages in view, the presentinvention will become more clearly understood in connection with thedetailed description of a preferred embodiment, when considered with theaccompanying drawings, of which:

FIG. 1 is a perspective view of a completed mold type semiconductordevice;

FIG. 2 is a sectional pictorial view of the prior art mold typesemiconductor device;

FIG. 3 is a partially enlarged view of the mold type semiconductordevice shown in FIG. 2;

FIGS. 4 ˜7 are views showing processes of a manufacturing methodaccording to this invention; in which

FIG. 4 is a partial sectional view of a semiconductor chip in the statewhere bump plating has been completed;

FIG. 5 is a partial sectional view of a semiconductor bump chip in thestate where wire bonding has been completed;

FIG. 6 is a partial sectional view of the completed semiconductordevice; and

FIG. 7 is a sectional view showing the entire completed semiconductordevice of FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED PROCESS OF THE INVENTION

The present method for manufacturing a semiconductor device with platedbumps is shown in FIGS. 4, 5, 6 and 7. Accordingly, semiconductor chip21 comprises not only a collector region 22 and a base region 23 butalso an oxide film 24 and an aluminium layer 25. Aluminium layer 25functions as wiring and is located at elevated, or bump formed,positions in the chip. An insulation layer, or film, 26 is applied onthe aluminium layer 25 by vapor growth, evaporation, sputtering or othersuitable techniques. Insulation film 26 comprises silicon oxide (SiO₂),for example, and has a thickness of 2μ˜3μ. After applying the insulationfilm 26, the film 26 is photo etched to make openings at the above bumpformed positions.

Then, a plating ground metal layer 27 is applied over the aluminiumlayer 25 and insulation film 26. Regarding this plating ground metal, itis required to use such metals that produce a strong adhesion force withthe aluminium layer 25 and insulation film 26, that have relativelysmall oxide generation energy, and that are easily bonded to the bumpforming plated layer mentioned later below. Chromium (Cr), copper (Cu)or gold (Au) can be used as the plating ground metal meet suchconditions. The plating ground metal layer 27 is applied over the wafersurface such that the layer 27 now comprises bonding pads together withthe bump forming plated layer. The plating ground metal layer 27 isapplied by evaporation or sputtering and has a thickness of 5000 Å˜8000Å depending on the grades of completed devices.

Then, to allow partial bump plating, a photo resist 28 is coated on theplating ground metal layer 27 in a thickness of about 2μ and openingsare made at bump formed positions in the photo resist 28 by patterntreatment.

Then, a bump forming plated layer 29 is applied at the bump formedpositions. The bump plating is carried out utilizing non-cyanic goldplating bath, but other materials may be substituted for non-cyanicgold. Thickness of the plated layer is in a range of 5μ˜25μ and isoptional according to the purpose of the completed semiconductordevices. When using non-cyanic gold plating bath, about 4 minutes isrequired for developing the plated layer of 1μ, in a normal platingvelocity and typical current density of 4 mA/cm². FIG. 4 shows thesemiconductor chip in the state where the forgoing processes have beencompleted.

Then, the photo resist 28, coated for bump plating, is lifted off andthe rest of the plating ground layer 27 is also removed except forleaving that part of layer 27 located at those bump formed positionsnecessary for the aluminium layer 25 and bump-forming plated layer 29 tobe closely bonded to the insulation film 26 and to be energized.Thereafter, a wire 31 is connected to the bump forming plated layer 29.At the end of this process, the semiconductor chip 32 as shown in FIG.5. is completed.

Then, after bonding the semiconductor chip 32 to a lead frame 33, thesemiconductor chip 32 is electrically connected with the lead frame 33through the wire 31 for energizing, so that a semiconductor bump chip 34is completed.

Then, for the purpose of passivation, passivation glass is vaporized byvacuum evaporation, vacuum sputtering or laser beam sputtering and thendeposited over the semiconductor bump chip 34 so as to form a depositionfilm 35. Thickness of the deposition film is suitable in a range of 5000Å˜50000 Å, and may be optional depending on the variety of semiconductordevice under consideration.

Finally, the whole chip is molded by sealing resin to form a resinmolded layer 36, so that a semiconductor device with plated bumps 37 iscompleted. FIGS. 6 and 7 show the DIP type resin molded semiconductordevice with plated bumps which has been manufactured in such a manner.

In addition, when utilizing a resist lifting off method, the chip ispattern-treated by using the photo resist coat identical to theforegoing photo resist 28 after forming the insulation film 26 and priorto applying the plating ground metal layer 27 as mentioned above.

Besides, although the wire 31 is used as the drawing out leads in theabove description by way of example, the wire 31 may be replaced byother type leads such as a drawing out lead formed by etching orpunching.

As described in the above, the semiconductor device with plated bumpsmade by the manufacturing method according to this invention has abetter seal than prior art devices and thus can be effectively used forelectric circuits that will be subjected to a stressful environmentcontaining moisture or harmful gas.

What is claimed is:
 1. A method of manufacturing a semiconductor devicewith plated bumps, the steps comprising:a first step in which aninsulation film with openings at bump formed positions is applied on asemiconductor wafer having aluminium wiring thereon, a second step inwhich a plating ground metal layer is formed on said insulation film, athird step in which a photo resist layer with openings at the bumpformed positions is masked over said plating ground metal layer, afourth step in which a metal which is easily bondable with drawn outleads is plated at the bump formed positions on said plating groundmetal layer to form bumps, a fifth step in which said photo resist layerand said plating ground metal layer located at those positions otherthan the bump formed positions are removed to complete a semiconductorchip, a sixth step in which drawn out leads are bonded to said bumps onsaid semiconductor chip to complete a semiconductor bump chip, a seventhstep in which said semiconductor bump chip is bonded to a connectingdevice, an eighth step in which said semiconductor bump chip and thepart of the connecting device to which it is bonded ispassivation-treated using passivation glass.
 2. A method ofmanufacturing a semiconductor device with plated bumps according toclaim 1, further comprising,prior to said second step, performing aninth step in which a photo resist layer with openings at bump formedpositions is masked over said insulation film, and wherein said platingground metal layer to be applied in said second step is first formed onsaid photo resist layer masked in said ninth step.
 3. A method ofmanufacturing a semiconductor device with plated bumps according toclaim 1, whereinforming in the eighth step, before a subsequent resinmolding step, a passivation deposition film in the range of 5,000 Å to50,000 Å on the semiconductor bump chip and the part of the connectingdevice to which it is bonded.
 4. A method of manufacturing asemiconductor device with plated bumps according to claim 3, furthercomprisingperforming a ninth step of resin molding molding the entiresemiconductor bump chip and the part of the connecting device to whichit is bonded with sealing resin after the eighth step.
 5. A method ofmanufacturing a semiconductor device with plated bumps according toclaim 1, further comprisingperforming a ninth step of resin moldingmolding the entire semiconductor bump chip and the part of theconnecting device to which it is bonded with sealing resin after theeighth step.
 6. A method of manufacturing a semiconductor device withplated bumps according to claim 1, whereinsaid eight step is performedby vaporizing the passivation glass by vacuum evaporation and depositingthe vaporized passivation glass over the semiconductor bump chip.
 7. Amethod of manufacturing a semiconductor device with plated bumpsaccording to claim 1, whereinsaid eight step is performed by vaporizingthe passivation glass by laser beam sputtering and then depositing thevaporized passivation glass over the semiconductor bump chip.
 8. Amethod of manufacturing a semiconductor device with plated bumpsaccording to claim 1, whereinsaid eight step is performed by vaporizingthe passivation glass by vacuum sputtering and then depositing thevaporized passivation glass over the semiconductor bump chip.
 9. Amethod of manufacturing a semiconductor device with plated bumpsaccording to claim 1, whereinthe connecting device is a lead frame. 10.A method of manufacturing a semiconductor device with plated bumpsaccording to claim 1, whereinthe connecting device is a circuitsubstrate.
 11. A method of manufacturing a semiconductor device withplated bumps according to claim 1, whereinbetween said seventh andeighth steps said drawn out leads are electrically connected to saidconnecting device.
 12. A method of manufacturing a semiconductor devicewith plated bumps according to claim 1, whereinsaid drawn out leads arewire.
 13. A method of manufacturing a semiconductor device with platedbumps according to claim 1, whereinthe bonding of the drawn out leads inthe sixth step is formed by etching.
 14. A method of manufacturing asemiconductor device with plated bumps according to claim 1, whereinthebonding of the drawn out leads in the sixth step is formed by punching.15. A method of manufacturing a semiconductor device with plated bumps,the steps comprising:a first step in which an insulation film withopenings at bump formed positions is applied on a semiconductor waferhaving aluminum wiring thereon, a second step in which a plating groundmetal layer is formed on said insulation film, a third step in which aphoto resist layer with openings at the bump formed positions is maskedover said plating ground metal layer, a fourth step in which a metalwhich is easily bondable with drawn out leads is plated at the bumpformed positions on said plating ground metal layer to form bumps, afifth step in which said photo resist layer and said plating groundmetal layer located at those positions other than the bump formedpositions are removed to complete a semiconductor chip, a sixth step inwhich said semiconductor chip is bonded to a lead frame or a circuitsubstrate, a seventh step in which drawn out leads are bonded to saidbumps on said semiconductor chip to complete a semiconductor bump chip,an eighth step in which said semiconductor bump chip ispassivation-treated using passivation glass.
 16. A method ofmanufacturing a semiconductor device with plated bumps according toclaim 15, whereinforming in the eighth step, before a subsequent resinmolding step, a passivation deposition film in the range of 5,000 Å to50,000 Å on the semiconductor bump chip.
 17. A method of manufacturing asemiconductor device with plated bumps according to claim 15, whereinthebonding of the drawn out leads in the sixth step is formed by etching.18. A method of manufacturing a semiconductor device with plated bumpsaccording to claim 1, whereinthe bonding of the drawn out leads in thesixth step is formed by punching.